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authorGravatar ReinUsesLisp2021-02-16 19:48:58 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit3a59fffaa16838985f9f953f30d1af4aa0f86252 (patch)
tree63d8dbf8cfb55da7c08233655fb6e87df18c4030
parentspirv: Initial bindings support (diff)
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spirv: Implement EmitIdentity
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.cpp4
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.cpp b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
index c79c09774..55018332e 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
@@ -180,8 +180,8 @@ Id EmitSPIRV::EmitPhi(EmitContext& ctx, IR::Inst* inst) {
180 180
181void EmitSPIRV::EmitVoid(EmitContext&) {} 181void EmitSPIRV::EmitVoid(EmitContext&) {}
182 182
183void EmitSPIRV::EmitIdentity(EmitContext&) { 183Id EmitSPIRV::EmitIdentity(EmitContext& ctx, const IR::Value& value) {
184 throw NotImplementedException("SPIR-V Instruction"); 184 return ctx.Def(value);
185} 185}
186 186
187void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) { 187void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) {
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index a5d0e1ec0..8bde82613 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -23,7 +23,7 @@ private:
23 // Microinstruction emitters 23 // Microinstruction emitters
24 Id EmitPhi(EmitContext& ctx, IR::Inst* inst); 24 Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
25 void EmitVoid(EmitContext& ctx); 25 void EmitVoid(EmitContext& ctx);
26 void EmitIdentity(EmitContext& ctx); 26 Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
27 void EmitBranch(EmitContext& ctx, IR::Block* label); 27 void EmitBranch(EmitContext& ctx, IR::Block* label);
28 void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label, 28 void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label,
29 IR::Block* false_label); 29 IR::Block* false_label);