diff options
| author | 2018-11-16 12:07:22 -0400 | |
|---|---|---|
| committer | 2018-11-24 13:25:54 -0400 | |
| commit | 33afff187056ca6ea4c1418d9dbabbdc888d710e (patch) | |
| tree | d209abb868ebdafbc62b6c96c77b4adccb474b92 | |
| parent | Merge pull request #1641 from DarkLordZach/sm-register-unregister (diff) | |
| download | yuzu-33afff187056ca6ea4c1418d9dbabbdc888d710e.tar.gz yuzu-33afff187056ca6ea4c1418d9dbabbdc888d710e.tar.xz yuzu-33afff187056ca6ea4c1418d9dbabbdc888d710e.zip | |
Implemented BRA CC conditional and FSET CC Setting
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 97b9028c5..df81286ea 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -3254,6 +3254,10 @@ private: | |||
| 3254 | regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1, | 3254 | regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1, |
| 3255 | 1); | 3255 | 1); |
| 3256 | } | 3256 | } |
| 3257 | if (instr.generates_cc.Value() != 0) { | ||
| 3258 | regs.SetInternalFlag(InternalFlag::ZeroFlag, predicate); | ||
| 3259 | LOG_WARNING(HW_GPU, "FSET Condition Code is incomplete"); | ||
| 3260 | } | ||
| 3257 | break; | 3261 | break; |
| 3258 | } | 3262 | } |
| 3259 | case OpCode::Type::IntegerSet: { | 3263 | case OpCode::Type::IntegerSet: { |
| @@ -3530,11 +3534,17 @@ private: | |||
| 3530 | "BRA with constant buffers are not implemented"); | 3534 | "BRA with constant buffers are not implemented"); |
| 3531 | 3535 | ||
| 3532 | const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; | 3536 | const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; |
| 3533 | UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, | ||
| 3534 | "BRA condition code used: {}", static_cast<u32>(cc)); | ||
| 3535 | |||
| 3536 | const u32 target = offset + instr.bra.GetBranchTarget(); | 3537 | const u32 target = offset + instr.bra.GetBranchTarget(); |
| 3537 | shader.AddLine("{ jmp_to = " + std::to_string(target) + "u; break; }"); | 3538 | if (cc != Tegra::Shader::ConditionCode::T) { |
| 3539 | const std::string condition_code = regs.GetConditionCode(cc); | ||
| 3540 | shader.AddLine("if (" + condition_code + "){"); | ||
| 3541 | shader.scope++; | ||
| 3542 | shader.AddLine("{ jmp_to = " + std::to_string(target) + "u; break; }"); | ||
| 3543 | shader.scope--; | ||
| 3544 | shader.AddLine('}'); | ||
| 3545 | } else { | ||
| 3546 | shader.AddLine("{ jmp_to = " + std::to_string(target) + "u; break; }"); | ||
| 3547 | } | ||
| 3538 | break; | 3548 | break; |
| 3539 | } | 3549 | } |
| 3540 | case OpCode::Id::IPA: { | 3550 | case OpCode::Id::IPA: { |