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| author | 2014-12-19 16:46:56 -0500 | |
|---|---|---|
| committer | 2014-12-19 16:46:56 -0500 | |
| commit | 245abb412501e231aee2fef5ffa96e728250edbb (patch) | |
| tree | 8b6144c1fdc3664d9f4ecff5a1e986e0dc6cb2ac | |
| parent | Merge pull request #305 from lioncash/paren (diff) | |
| parent | armemu: Narrow the scope of some variables in handle_v6_insn (diff) | |
| download | yuzu-245abb412501e231aee2fef5ffa96e728250edbb.tar.gz yuzu-245abb412501e231aee2fef5ffa96e728250edbb.tar.xz yuzu-245abb412501e231aee2fef5ffa96e728250edbb.zip | |
Merge pull request #294 from lioncash/var
armemu: Narrow the scope of some variables in handle_v6_insn
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 21 |
1 files changed, 9 insertions, 12 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 56040a4eb..63cfd03c6 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp | |||
| @@ -5681,11 +5681,8 @@ L_stm_s_takeabort: | |||
| 5681 | /* Attempt to emulate an ARMv6 instruction. | 5681 | /* Attempt to emulate an ARMv6 instruction. |
| 5682 | Returns non-zero upon success. */ | 5682 | Returns non-zero upon success. */ |
| 5683 | 5683 | ||
| 5684 | static int | 5684 | static int handle_v6_insn(ARMul_State* state, ARMword instr) { |
| 5685 | handle_v6_insn (ARMul_State * state, ARMword instr) { | 5685 | switch (BITS(20, 27)) { |
| 5686 | ARMword lhs, temp; | ||
| 5687 | |||
| 5688 | switch (BITS (20, 27)) { | ||
| 5689 | case 0x03: | 5686 | case 0x03: |
| 5690 | printf ("Unhandled v6 insn: ldr\n"); | 5687 | printf ("Unhandled v6 insn: ldr\n"); |
| 5691 | break; | 5688 | break; |
| @@ -5719,7 +5716,7 @@ L_stm_s_takeabort: | |||
| 5719 | /* strex */ | 5716 | /* strex */ |
| 5720 | u32 l = LHSReg; | 5717 | u32 l = LHSReg; |
| 5721 | u32 r = RHSReg; | 5718 | u32 r = RHSReg; |
| 5722 | lhs = LHS; | 5719 | u32 lhs = LHS; |
| 5723 | 5720 | ||
| 5724 | bool enter = false; | 5721 | bool enter = false; |
| 5725 | 5722 | ||
| @@ -5744,7 +5741,7 @@ L_stm_s_takeabort: | |||
| 5744 | case 0x19: | 5741 | case 0x19: |
| 5745 | /* ldrex */ | 5742 | /* ldrex */ |
| 5746 | if (BITS(4, 7) == 0x9) { | 5743 | if (BITS(4, 7) == 0x9) { |
| 5747 | lhs = LHS; | 5744 | u32 lhs = LHS; |
| 5748 | 5745 | ||
| 5749 | state->currentexaddr = lhs; | 5746 | state->currentexaddr = lhs; |
| 5750 | state->currentexval = ARMul_ReadWord(state, lhs); | 5747 | state->currentexval = ARMul_ReadWord(state, lhs); |
| @@ -5763,7 +5760,7 @@ L_stm_s_takeabort: | |||
| 5763 | case 0x1c: | 5760 | case 0x1c: |
| 5764 | if (BITS(4, 7) == 0x9) { | 5761 | if (BITS(4, 7) == 0x9) { |
| 5765 | /* strexb */ | 5762 | /* strexb */ |
| 5766 | lhs = LHS; | 5763 | u32 lhs = LHS; |
| 5767 | 5764 | ||
| 5768 | bool enter = false; | 5765 | bool enter = false; |
| 5769 | 5766 | ||
| @@ -5793,11 +5790,11 @@ L_stm_s_takeabort: | |||
| 5793 | case 0x1d: | 5790 | case 0x1d: |
| 5794 | if ((BITS(4, 7)) == 0x9) { | 5791 | if ((BITS(4, 7)) == 0x9) { |
| 5795 | /* ldrexb */ | 5792 | /* ldrexb */ |
| 5796 | temp = LHS; | 5793 | u32 lhs = LHS; |
| 5797 | LoadByte(state, instr, temp, LUNSIGNED); | 5794 | LoadByte(state, instr, lhs, LUNSIGNED); |
| 5798 | 5795 | ||
| 5799 | state->currentexaddr = temp; | 5796 | state->currentexaddr = lhs; |
| 5800 | state->currentexval = (u32)ARMul_ReadByte(state, temp); | 5797 | state->currentexval = (u32)ARMul_ReadByte(state, lhs); |
| 5801 | 5798 | ||
| 5802 | //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]); | 5799 | //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]); |
| 5803 | //printf("ldrexb\n"); | 5800 | //printf("ldrexb\n"); |