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| author | 2018-12-17 18:49:48 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:52 -0300 | |
| commit | 210620ff314c774cd0da5a6b50501dec45914751 (patch) | |
| tree | ebe61d192550b2bdfab39bf82c27f0f86eeddbfe | |
| parent | shader_decode: Implement XMAD (diff) | |
| download | yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.gz yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.xz yuzu-210620ff314c774cd0da5a6b50501dec45914751.zip | |
shader_decode: Implement ISCADD
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index d01336e0e..d494af736 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp | |||
| @@ -41,6 +41,21 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) { | |||
| 41 | SetRegister(bb, instr.gpr0, Operation(OperationCode::IAdd, PRECISE, op_a, op_b)); | 41 | SetRegister(bb, instr.gpr0, Operation(OperationCode::IAdd, PRECISE, op_a, op_b)); |
| 42 | break; | 42 | break; |
| 43 | } | 43 | } |
| 44 | case OpCode::Id::ISCADD_C: | ||
| 45 | case OpCode::Id::ISCADD_R: | ||
| 46 | case OpCode::Id::ISCADD_IMM: { | ||
| 47 | UNIMPLEMENTED_IF_MSG(instr.generates_cc, | ||
| 48 | "Condition codes generation in ISCADD is not implemented"); | ||
| 49 | |||
| 50 | op_a = GetOperandAbsNegInteger(op_a, false, instr.alu_integer.negate_a, true); | ||
| 51 | op_b = GetOperandAbsNegInteger(op_b, false, instr.alu_integer.negate_b, true); | ||
| 52 | |||
| 53 | const Node shift = Immediate(static_cast<u32>(instr.alu_integer.shift_amount)); | ||
| 54 | const Node shifted_a = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, op_a, shift); | ||
| 55 | const Node value = Operation(OperationCode::IAdd, NO_PRECISE, shifted_a, op_b); | ||
| 56 | SetRegister(bb, instr.gpr0, value); | ||
| 57 | break; | ||
| 58 | } | ||
| 44 | case OpCode::Id::SEL_C: | 59 | case OpCode::Id::SEL_C: |
| 45 | case OpCode::Id::SEL_R: | 60 | case OpCode::Id::SEL_R: |
| 46 | case OpCode::Id::SEL_IMM: { | 61 | case OpCode::Id::SEL_IMM: { |