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authorGravatar Mathew Maidment2015-12-23 04:56:04 -0500
committerGravatar Mathew Maidment2015-12-23 04:56:04 -0500
commit031443199bf5df2fc1f840793b36b975a61a5596 (patch)
tree522de18165c3999d7434f1f22b324c50a9ace238
parentMerge pull request #1289 from yuriks/reset-rasterizer (diff)
parentdyncom: Remove PC dispatch from several instructions (diff)
downloadyuzu-031443199bf5df2fc1f840793b36b975a61a5596.tar.gz
yuzu-031443199bf5df2fc1f840793b36b975a61a5596.tar.xz
yuzu-031443199bf5df2fc1f840793b36b975a61a5596.zip
Merge pull request #1287 from lioncash/memory
dyncom: Minor changes
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp126
1 files changed, 29 insertions, 97 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 2cff2a26a..459877eae 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -1623,9 +1623,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index)
1623 inst_cream->inst = inst; 1623 inst_cream->inst = inst;
1624 inst_cream->get_addr = get_calc_addr_op(inst); 1624 inst_cream->get_addr = get_calc_addr_op(inst);
1625 1625
1626 if (BITS(inst, 12, 15) == 15) {
1627 inst_base->br = INDIRECT_BRANCH;
1628 }
1629 return inst_base; 1626 return inst_base;
1630} 1627}
1631static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) 1628static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index)
@@ -1646,9 +1643,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index)
1646 DEBUG_MSG; 1643 DEBUG_MSG;
1647 } 1644 }
1648 1645
1649 if (BITS(inst, 12, 15) == 15) {
1650 inst_base->br = INDIRECT_BRANCH;
1651 }
1652 return inst_base; 1646 return inst_base;
1653} 1647}
1654static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) 1648static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index)
@@ -1703,9 +1697,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index)
1703 inst_cream->inst = inst; 1697 inst_cream->inst = inst;
1704 inst_cream->get_addr = get_calc_addr_op(inst); 1698 inst_cream->get_addr = get_calc_addr_op(inst);
1705 1699
1706 if (BITS(inst, 12, 15) == 15) {
1707 inst_base->br = INDIRECT_BRANCH;
1708 }
1709 return inst_base; 1700 return inst_base;
1710} 1701}
1711static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) 1702static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index)
@@ -1720,9 +1711,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index)
1720 inst_cream->inst = inst; 1711 inst_cream->inst = inst;
1721 inst_cream->get_addr = get_calc_addr_op(inst); 1712 inst_cream->get_addr = get_calc_addr_op(inst);
1722 1713
1723 if (BITS(inst, 12, 15) == 15) {
1724 inst_base->br = INDIRECT_BRANCH;
1725 }
1726 return inst_base; 1714 return inst_base;
1727} 1715}
1728static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) 1716static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index)
@@ -1737,9 +1725,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index)
1737 inst_cream->inst = inst; 1725 inst_cream->inst = inst;
1738 inst_cream->get_addr = get_calc_addr_op(inst); 1726 inst_cream->get_addr = get_calc_addr_op(inst);
1739 1727
1740 if (BITS(inst, 12, 15) == 15) {
1741 inst_base->br = INDIRECT_BRANCH;
1742 }
1743 return inst_base; 1728 return inst_base;
1744} 1729}
1745static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) 1730static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
@@ -2597,9 +2582,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index)
2597 inst_cream->inst = inst; 2582 inst_cream->inst = inst;
2598 inst_cream->get_addr = get_calc_addr_op(inst); 2583 inst_cream->get_addr = get_calc_addr_op(inst);
2599 2584
2600 if (BITS(inst, 12, 15) == 15) {
2601 inst_base->br = INDIRECT_BRANCH;
2602 }
2603 return inst_base; 2585 return inst_base;
2604} 2586}
2605static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) 2587static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index)
@@ -2645,9 +2627,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index)
2645 inst_cream->inst = inst; 2627 inst_cream->inst = inst;
2646 inst_cream->get_addr = get_calc_addr_op(inst); 2628 inst_cream->get_addr = get_calc_addr_op(inst);
2647 2629
2648 if (BITS(inst, 12, 15) == 15) {
2649 inst_base->br = INDIRECT_BRANCH;
2650 }
2651 return inst_base; 2630 return inst_base;
2652} 2631}
2653static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) 2632static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index)
@@ -2669,9 +2648,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index)
2669 DEBUG_MSG; 2648 DEBUG_MSG;
2670 } 2649 }
2671 2650
2672 if (BITS(inst, 12, 15) == 15) {
2673 inst_base->br = INDIRECT_BRANCH;
2674 }
2675 return inst_base; 2651 return inst_base;
2676} 2652}
2677static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ 2653static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){
@@ -2685,9 +2661,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){
2685 inst_cream->inst = inst; 2661 inst_cream->inst = inst;
2686 inst_cream->get_addr = get_calc_addr_op(inst); 2662 inst_cream->get_addr = get_calc_addr_op(inst);
2687 2663
2688 if (BITS(inst, 12, 15) == 15) {
2689 inst_base->br = INDIRECT_BRANCH;
2690 }
2691 return inst_base; 2664 return inst_base;
2692} 2665}
2693static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) 2666static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index)
@@ -2729,9 +2702,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index)
2729 inst_cream->inst = inst; 2702 inst_cream->inst = inst;
2730 inst_cream->get_addr = get_calc_addr_op(inst); 2703 inst_cream->get_addr = get_calc_addr_op(inst);
2731 2704
2732 if (BITS(inst, 12, 15) == 15) {
2733 inst_base->br = INDIRECT_BRANCH;
2734 }
2735 return inst_base; 2705 return inst_base;
2736} 2706}
2737static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) 2707static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
@@ -2757,9 +2727,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
2757 DEBUG_MSG; 2727 DEBUG_MSG;
2758 } 2728 }
2759 2729
2760 if (BITS(inst, 12, 15) == 15) {
2761 inst_base->br = INDIRECT_BRANCH;
2762 }
2763 return inst_base; 2730 return inst_base;
2764} 2731}
2765static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) 2732static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index)
@@ -2808,9 +2775,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index)
2808 inst_cream->Rd = BITS(inst, 12, 15); 2775 inst_cream->Rd = BITS(inst, 12, 15);
2809 inst_cream->Rm = BITS(inst, 0, 3); 2776 inst_cream->Rm = BITS(inst, 0, 3);
2810 2777
2811 if (inst_cream->Rd == 15) {
2812 inst_base->br = INDIRECT_BRANCH;
2813 }
2814 return inst_base; 2778 return inst_base;
2815} 2779}
2816static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ 2780static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){
@@ -2825,9 +2789,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){
2825 inst_cream->Rd = BITS(inst, 12, 15); 2789 inst_cream->Rd = BITS(inst, 12, 15);
2826 inst_cream->Rm = BITS(inst, 0, 3); 2790 inst_cream->Rm = BITS(inst, 0, 3);
2827 2791
2828 if (inst_cream->Rd == 15) {
2829 inst_base->br = INDIRECT_BRANCH;
2830 }
2831 return inst_base; 2792 return inst_base;
2832} 2793}
2833static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ 2794static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){
@@ -2915,9 +2876,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index)
2915 inst_cream->shifter_operand = BITS(inst, 0, 11); 2876 inst_cream->shifter_operand = BITS(inst, 0, 11);
2916 inst_cream->shtop_func = get_shtop(inst); 2877 inst_cream->shtop_func = get_shtop(inst);
2917 2878
2918 if (inst_cream->Rd == 15)
2919 inst_base->br = INDIRECT_BRANCH;
2920
2921 return inst_base; 2879 return inst_base;
2922} 2880}
2923 2881
@@ -4477,11 +4435,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4477 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4435 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4478 4436
4479 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr); 4437 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr);
4480
4481 if (BITS(inst_cream->inst, 12, 15) == 15) {
4482 INC_PC(sizeof(ldst_inst));
4483 goto DISPATCH;
4484 }
4485 } 4438 }
4486 cpu->Reg[15] += cpu->GetInstructionSize(); 4439 cpu->Reg[15] += cpu->GetInstructionSize();
4487 INC_PC(sizeof(ldst_inst)); 4440 INC_PC(sizeof(ldst_inst));
@@ -4494,12 +4447,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4494 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4447 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4495 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4448 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4496 4449
4497 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr); 4450 const u32 dest_index = BITS(inst_cream->inst, 12, 15);
4451 const u32 previous_mode = cpu->Mode;
4498 4452
4499 if (BITS(inst_cream->inst, 12, 15) == 15) { 4453 cpu->ChangePrivilegeMode(USER32MODE);
4500 INC_PC(sizeof(ldst_inst)); 4454 const u8 value = cpu->ReadMemory8(addr);
4501 goto DISPATCH; 4455 cpu->ChangePrivilegeMode(previous_mode);
4502 } 4456
4457 cpu->Reg[dest_index] = value;
4503 } 4458 }
4504 cpu->Reg[15] += cpu->GetInstructionSize(); 4459 cpu->Reg[15] += cpu->GetInstructionSize();
4505 INC_PC(sizeof(ldst_inst)); 4460 INC_PC(sizeof(ldst_inst));
@@ -4535,10 +4490,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4535 cpu->SetExclusiveMemoryAddress(read_addr); 4490 cpu->SetExclusiveMemoryAddress(read_addr);
4536 4491
4537 RD = cpu->ReadMemory32(read_addr); 4492 RD = cpu->ReadMemory32(read_addr);
4538 if (inst_cream->Rd == 15) {
4539 INC_PC(sizeof(generic_arm_inst));
4540 goto DISPATCH;
4541 }
4542 } 4493 }
4543 cpu->Reg[15] += cpu->GetInstructionSize(); 4494 cpu->Reg[15] += cpu->GetInstructionSize();
4544 INC_PC(sizeof(generic_arm_inst)); 4495 INC_PC(sizeof(generic_arm_inst));
@@ -4554,10 +4505,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4554 cpu->SetExclusiveMemoryAddress(read_addr); 4505 cpu->SetExclusiveMemoryAddress(read_addr);
4555 4506
4556 RD = cpu->ReadMemory8(read_addr); 4507 RD = cpu->ReadMemory8(read_addr);
4557 if (inst_cream->Rd == 15) {
4558 INC_PC(sizeof(generic_arm_inst));
4559 goto DISPATCH;
4560 }
4561 } 4508 }
4562 cpu->Reg[15] += cpu->GetInstructionSize(); 4509 cpu->Reg[15] += cpu->GetInstructionSize();
4563 INC_PC(sizeof(generic_arm_inst)); 4510 INC_PC(sizeof(generic_arm_inst));
@@ -4573,10 +4520,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4573 cpu->SetExclusiveMemoryAddress(read_addr); 4520 cpu->SetExclusiveMemoryAddress(read_addr);
4574 4521
4575 RD = cpu->ReadMemory16(read_addr); 4522 RD = cpu->ReadMemory16(read_addr);
4576 if (inst_cream->Rd == 15) {
4577 INC_PC(sizeof(generic_arm_inst));
4578 goto DISPATCH;
4579 }
4580 } 4523 }
4581 cpu->Reg[15] += cpu->GetInstructionSize(); 4524 cpu->Reg[15] += cpu->GetInstructionSize();
4582 INC_PC(sizeof(generic_arm_inst)); 4525 INC_PC(sizeof(generic_arm_inst));
@@ -4593,11 +4536,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4593 4536
4594 RD = cpu->ReadMemory32(read_addr); 4537 RD = cpu->ReadMemory32(read_addr);
4595 RD2 = cpu->ReadMemory32(read_addr + 4); 4538 RD2 = cpu->ReadMemory32(read_addr + 4);
4596
4597 if (inst_cream->Rd == 15) {
4598 INC_PC(sizeof(generic_arm_inst));
4599 goto DISPATCH;
4600 }
4601 } 4539 }
4602 cpu->Reg[15] += cpu->GetInstructionSize(); 4540 cpu->Reg[15] += cpu->GetInstructionSize();
4603 INC_PC(sizeof(generic_arm_inst)); 4541 INC_PC(sizeof(generic_arm_inst));
@@ -4611,10 +4549,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4611 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4549 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4612 4550
4613 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr); 4551 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr);
4614 if (BITS(inst_cream->inst, 12, 15) == 15) {
4615 INC_PC(sizeof(ldst_inst));
4616 goto DISPATCH;
4617 }
4618 } 4552 }
4619 cpu->Reg[15] += cpu->GetInstructionSize(); 4553 cpu->Reg[15] += cpu->GetInstructionSize();
4620 INC_PC(sizeof(ldst_inst)); 4554 INC_PC(sizeof(ldst_inst));
@@ -4631,10 +4565,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4631 value |= 0xffffff00; 4565 value |= 0xffffff00;
4632 } 4566 }
4633 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4567 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4634 if (BITS(inst_cream->inst, 12, 15) == 15) {
4635 INC_PC(sizeof(ldst_inst));
4636 goto DISPATCH;
4637 }
4638 } 4568 }
4639 cpu->Reg[15] += cpu->GetInstructionSize(); 4569 cpu->Reg[15] += cpu->GetInstructionSize();
4640 INC_PC(sizeof(ldst_inst)); 4570 INC_PC(sizeof(ldst_inst));
@@ -4652,10 +4582,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4652 value |= 0xffff0000; 4582 value |= 0xffff0000;
4653 } 4583 }
4654 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4584 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4655 if (BITS(inst_cream->inst, 12, 15) == 15) {
4656 INC_PC(sizeof(ldst_inst));
4657 goto DISPATCH;
4658 }
4659 } 4585 }
4660 cpu->Reg[15] += cpu->GetInstructionSize(); 4586 cpu->Reg[15] += cpu->GetInstructionSize();
4661 INC_PC(sizeof(ldst_inst)); 4587 INC_PC(sizeof(ldst_inst));
@@ -4668,13 +4594,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4668 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4594 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4669 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4595 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4670 4596
4671 unsigned int value = cpu->ReadMemory32(addr); 4597 const u32 dest_index = BITS(inst_cream->inst, 12, 15);
4672 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4598 const u32 previous_mode = cpu->Mode;
4673 4599
4674 if (BITS(inst_cream->inst, 12, 15) == 15) { 4600 cpu->ChangePrivilegeMode(USER32MODE);
4675 INC_PC(sizeof(ldst_inst)); 4601 const u32 value = cpu->ReadMemory32(addr);
4676 goto DISPATCH; 4602 cpu->ChangePrivilegeMode(previous_mode);
4677 } 4603
4604 cpu->Reg[dest_index] = value;
4678 } 4605 }
4679 cpu->Reg[15] += cpu->GetInstructionSize(); 4606 cpu->Reg[15] += cpu->GetInstructionSize();
4680 INC_PC(sizeof(ldst_inst)); 4607 INC_PC(sizeof(ldst_inst));
@@ -4731,10 +4658,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4731 UPDATE_NFLAG(RD); 4658 UPDATE_NFLAG(RD);
4732 UPDATE_ZFLAG(RD); 4659 UPDATE_ZFLAG(RD);
4733 } 4660 }
4734 if (inst_cream->Rd == 15) {
4735 INC_PC(sizeof(mla_inst));
4736 goto DISPATCH;
4737 }
4738 } 4661 }
4739 cpu->Reg[15] += cpu->GetInstructionSize(); 4662 cpu->Reg[15] += cpu->GetInstructionSize();
4740 INC_PC(sizeof(mla_inst)); 4663 INC_PC(sizeof(mla_inst));
@@ -4883,10 +4806,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4883 UPDATE_NFLAG(RD); 4806 UPDATE_NFLAG(RD);
4884 UPDATE_ZFLAG(RD); 4807 UPDATE_ZFLAG(RD);
4885 } 4808 }
4886 if (inst_cream->Rd == 15) {
4887 INC_PC(sizeof(mul_inst));
4888 goto DISPATCH;
4889 }
4890 } 4809 }
4891 cpu->Reg[15] += cpu->GetInstructionSize(); 4810 cpu->Reg[15] += cpu->GetInstructionSize();
4892 INC_PC(sizeof(mul_inst)); 4811 INC_PC(sizeof(mul_inst));
@@ -6061,8 +5980,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6061 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 5980 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
6062 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 5981 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6063 inst_cream->get_addr(cpu, inst_cream->inst, addr); 5982 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6064 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 5983
5984 const u32 previous_mode = cpu->Mode;
5985 const u32 value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
5986
5987 cpu->ChangePrivilegeMode(USER32MODE);
6065 cpu->WriteMemory8(addr, value); 5988 cpu->WriteMemory8(addr, value);
5989 cpu->ChangePrivilegeMode(previous_mode);
6066 } 5990 }
6067 cpu->Reg[15] += cpu->GetInstructionSize(); 5991 cpu->Reg[15] += cpu->GetInstructionSize();
6068 INC_PC(sizeof(ldst_inst)); 5992 INC_PC(sizeof(ldst_inst));
@@ -6196,8 +6120,16 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6196 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6120 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6197 inst_cream->get_addr(cpu, inst_cream->inst, addr); 6121 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6198 6122
6199 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 6123 const u32 previous_mode = cpu->Mode;
6124 const u32 rt_index = BITS(inst_cream->inst, 12, 15);
6125
6126 u32 value = cpu->Reg[rt_index];
6127 if (rt_index == 15)
6128 value += 2 * cpu->GetInstructionSize();
6129
6130 cpu->ChangePrivilegeMode(USER32MODE);
6200 cpu->WriteMemory32(addr, value); 6131 cpu->WriteMemory32(addr, value);
6132 cpu->ChangePrivilegeMode(previous_mode);
6201 } 6133 }
6202 cpu->Reg[15] += cpu->GetInstructionSize(); 6134 cpu->Reg[15] += cpu->GetInstructionSize();
6203 INC_PC(sizeof(ldst_inst)); 6135 INC_PC(sizeof(ldst_inst));