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| author |  Yuri Kunde Schlesner | 2015-07-18 03:14:56 -0300 |
|---|---|---|
| committer | Yuri Kunde Schlesner | 2015-07-18 03:41:49 -0300 |
| commit | 13286903e6ca4daae8814b0e709cc691f6a06f10 (patch) | |
| tree | c77a90557a7d957d86ab90b994b2eea33e3eceaa | |
| parent | Merge pull request #938 from Subv/querymem (diff) | |
| download | yuzu-13286903e6ca4daae8814b0e709cc691f6a06f10.tar.gz yuzu-13286903e6ca4daae8814b0e709cc691f6a06f10.tar.xz yuzu-13286903e6ca4daae8814b0e709cc691f6a06f10.zip | |
Dyncom: Support for a missing ARMv6 Thumb MOV encoding
Diffstat (limited to '')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_thumb.cpp | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index 3e79c44c0..f10a5b70f 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp | |||
| @@ -130,14 +130,13 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { | |||
| 130 | } | 130 | } |
| 131 | } else { | 131 | } else { |
| 132 | ARMword Rd = ((tinstr & 0x0007) >> 0); | 132 | ARMword Rd = ((tinstr & 0x0007) >> 0); |
| 133 | ARMword Rs = ((tinstr & 0x0038) >> 3); | 133 | ARMword Rs = ((tinstr & 0x0078) >> 3); |
| 134 | 134 | ||
| 135 | if (tinstr & (1 << 7)) | 135 | if (tinstr & (1 << 7)) |
| 136 | Rd += 8; | 136 | Rd += 8; |
| 137 | if (tinstr & (1 << 6)) | ||
| 138 | Rs += 8; | ||
| 139 | 137 | ||
| 140 | switch ((tinstr & 0x03C0) >> 6) { | 138 | switch ((tinstr & 0x03C0) >> 6) { |
| 139 | case 0x0: // ADD Rd,Rd,Rs | ||
| 141 | case 0x1: // ADD Rd,Rd,Hs | 140 | case 0x1: // ADD Rd,Rd,Hs |
| 142 | case 0x2: // ADD Hd,Hd,Rs | 141 | case 0x2: // ADD Hd,Hd,Rs |
| 143 | case 0x3: // ADD Hd,Hd,Hs | 142 | case 0x3: // ADD Hd,Hd,Hs |
| @@ -146,19 +145,19 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { | |||
| 146 | |(Rd << 12) // Rd | 145 | |(Rd << 12) // Rd |
| 147 | |(Rs << 0); // Rm | 146 | |(Rs << 0); // Rm |
| 148 | break; | 147 | break; |
| 148 | case 0x4: // CMP Rd,Rs | ||
| 149 | case 0x5: // CMP Rd,Hs | 149 | case 0x5: // CMP Rd,Hs |
| 150 | case 0x6: // CMP Hd,Rs | 150 | case 0x6: // CMP Hd,Rs |
| 151 | case 0x7: // CMP Hd,Hs | 151 | case 0x7: // CMP Hd,Hs |
| 152 | *ainstr = 0xE1500000 // base | 152 | *ainstr = 0xE1500000 // base |
| 153 | | (Rd << 16) // Rn | 153 | | (Rd << 16) // Rn |
| 154 | |(Rd << 12) // Rd | ||
| 155 | |(Rs << 0); // Rm | 154 | |(Rs << 0); // Rm |
| 156 | break; | 155 | break; |
| 156 | case 0x8: // MOV Rd,Rs | ||
| 157 | case 0x9: // MOV Rd,Hs | 157 | case 0x9: // MOV Rd,Hs |
| 158 | case 0xA: // MOV Hd,Rs | 158 | case 0xA: // MOV Hd,Rs |
| 159 | case 0xB: // MOV Hd,Hs | 159 | case 0xB: // MOV Hd,Hs |
| 160 | *ainstr = 0xE1A00000 // base | 160 | *ainstr = 0xE1A00000 // base |
| 161 | | (Rd << 16) // Rn | ||
| 162 | |(Rd << 12) // Rd | 161 | |(Rd << 12) // Rd |
| 163 | |(Rs << 0); // Rm | 162 | |(Rs << 0); // Rm |
| 164 | break; | 163 | break; |
| @@ -167,11 +166,6 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { | |||
| 167 | *ainstr = 0xE12FFF10 // base | 166 | *ainstr = 0xE12FFF10 // base |
| 168 | | ((tinstr & 0x0078) >> 3); // Rd | 167 | | ((tinstr & 0x0078) >> 3); // Rd |
| 169 | break; | 168 | break; |
| 170 | case 0x0: // UNDEFINED | ||
| 171 | case 0x4: // UNDEFINED | ||
| 172 | case 0x8: // UNDEFINED | ||
| 173 | valid = t_undefined; | ||
| 174 | break; | ||
| 175 | case 0xE: // BLX | 169 | case 0xE: // BLX |
| 176 | case 0xF: // BLX | 170 | case 0xF: // BLX |
| 177 | *ainstr = 0xE1200030 // base | 171 | *ainstr = 0xE1200030 // base |