diff options
| author | 2019-10-31 01:56:29 +0000 | |
|---|---|---|
| committer | 2019-10-31 01:56:29 +0000 | |
| commit | 11e39da02bec92fe4a332bfb737323ccb8087626 (patch) | |
| tree | 4e206c28928fbda8e4e82ee7c377c6dcb6e992b6 | |
| parent | Merge pull request #3050 from FernandoS27/fix-tld4 (diff) | |
| parent | Shader_IR: Fix regression on TLD4 (diff) | |
| download | yuzu-11e39da02bec92fe4a332bfb737323ccb8087626.tar.gz yuzu-11e39da02bec92fe4a332bfb737323ccb8087626.tar.xz yuzu-11e39da02bec92fe4a332bfb737323ccb8087626.zip | |
Merge pull request #3054 from FernandoS27/fix-tld4-2
shader_ir: Fix regression on TLD4
Diffstat (limited to '')
| -rw-r--r-- | src/video_core/shader/decode/texture.cpp | 7 | ||||
| -rw-r--r-- | src/video_core/shader/shader_ir.h | 2 |
2 files changed, 4 insertions, 5 deletions
diff --git a/src/video_core/shader/decode/texture.cpp b/src/video_core/shader/decode/texture.cpp index 0599ef34f..4c838c8bb 100644 --- a/src/video_core/shader/decode/texture.cpp +++ b/src/video_core/shader/decode/texture.cpp | |||
| @@ -119,7 +119,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 119 | : instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI); | 119 | : instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI); |
| 120 | WriteTexInstructionFloat( | 120 | WriteTexInstructionFloat( |
| 121 | bb, instr, | 121 | bb, instr, |
| 122 | GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi, is_bindless), true); | 122 | GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi, is_bindless)); |
| 123 | break; | 123 | break; |
| 124 | } | 124 | } |
| 125 | case OpCode::Id::TLD4S: { | 125 | case OpCode::Id::TLD4S: { |
| @@ -366,11 +366,10 @@ const Sampler& ShaderIR::GetBindlessSampler(const Tegra::Shader::Register& reg, | |||
| 366 | return *used_samplers.emplace(entry).first; | 366 | return *used_samplers.emplace(entry).first; |
| 367 | } | 367 | } |
| 368 | 368 | ||
| 369 | void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components, | 369 | void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) { |
| 370 | bool is_tld4) { | ||
| 371 | u32 dest_elem = 0; | 370 | u32 dest_elem = 0; |
| 372 | for (u32 elem = 0; elem < 4; ++elem) { | 371 | for (u32 elem = 0; elem < 4; ++elem) { |
| 373 | if (!is_tld4 && !instr.tex.IsComponentEnabled(elem)) { | 372 | if (!instr.tex.IsComponentEnabled(elem)) { |
| 374 | // Skip disabled components | 373 | // Skip disabled components |
| 375 | continue; | 374 | continue; |
| 376 | } | 375 | } |
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index 7582999a5..b5567f54e 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h | |||
| @@ -326,7 +326,7 @@ private: | |||
| 326 | Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits); | 326 | Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits); |
| 327 | 327 | ||
| 328 | void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, | 328 | void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, |
| 329 | const Node4& components, bool is_tld4 = false); | 329 | const Node4& components); |
| 330 | 330 | ||
| 331 | void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, | 331 | void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, |
| 332 | const Node4& components, bool ignore_mask = false); | 332 | const Node4& components, bool ignore_mask = false); |